Comprehensive Hardware and Software Support for Operating Systems to Exploit MP Memory Hierarchies

High-performance multiprocessor workstations are becoming increasingly popular. Since many of the workloads running on these machines are operating-system intensive, we are interested in what sort of support for the operating system should the memory hierarchy of these machines provide. This paper addresses this question. This paper shows that the largest performance losses for the operating system in a sophisticated 3-level cache hierarchy are due to oo-chip cache misses, write buuer overrow in block operations, and instruction connicts in the primary cache. To overcome these problems, we evaluate a comprehensive set of hardware and software supports. These supports, selected from recent papers, are code layout optimization, guarded sequential instruction prefetching, instruction stream buuers, support for block operations, support for coherence activity, and software data prefetching. We evaluate these supports under a uniform environment. We show that they target the problems indicated above, have a largely complementary impact and, when combined, speed up the operating system by an average of 32%. Finally, a cost-performance comparison of these schemes shows that the most cost-eeective ones are block operation support and code layout optimization, while the least cost-eeective one is software data prefetching.